The invention is related to a CMOS input circuit.
The use of CMOS input circuits is widespread as such circuits are very frequently used in integrated circuits. As the integration density of such circuits increases and thus the device geometries decrease, significant parameter spreads occur. The noise induced by large currents flowing in ground- and supply lines may contribute to the difficulties in sensing logic (e.g. TTL-) one and zero levels. A tight control over the input switching thresholds is especially desirable.
Several solutions have been proposed, such as a CMOS-inverter, which is biassed from the positive and negative circuit supply terminals, such that the input threshold switching level of the CMOS-inverter is substantially independent of CMOS-device characteristics tolerance (See GB patent application No. 2.133.242A). The biassing means include a P- and an N-channel transistor, the P-channel transistor is connected between the N-channel transistor of the inverter and the negative supply terminal, and the N-channel transistor is connected between the P-channel transistor of the inverter and the positive supply terminal. The gates of the biassing P-channel and N-channel transistor are connected to the negative and the positive supply terminal respectively. Although the CMOS-input circuit according to the prior art has a switching threshold, which is substantially independent from transistor characteristics, the input circuit is hampered with some drawbacks. Notably the use of additional transistors, especially P-channel transistors, increases the circuit area on the semiconductor chip, on which the circuit is to be integrated. Further the use of the biassing transistors adds an offset to the N-type transistor of the inverter equal to the P-type transistor threshold and an off set to the P-transistor of the inverter equal to the N-type transistor threshold, which renders the prior art input circuit unsuitable for TTL-level input signals and for use with low power supply voltages (e.g. 2-2.5 L Volt).